1. Technical Field
The present invention is generally directed to clock signals. More specifically, the present invention is directed to a variable pulse width and pulse separation clock generator.
2. Description of Related Art
Dynamic logic is extensively being used in designing high-speed complementary metal oxide semi-conductor (CMOS) circuits. Dynamic logic circuits are clocked circuits. Specifically, a dynamic logic circuit is a structure that includes an output node, a number of NMOS devices and at least one PMOS device. The PMOS device has its gate coupled to a clock for receiving a clock signal, its source coupled to a high voltage Vcc and its drain coupled to a dynamic node. When the clock signal is low, the PMOS device is turned on and the dynamic node is pre-charged to the high voltage Vcc.
In certain dynamic logic circuits (e.g., OR-gates), each NMOS device may have its source coupled to ground or to a low voltage Vss, its drain coupled to the dynamic node and its gate enabled to receive an input signal. Thus, the NMOS devices may conditionally discharge the dynamic node to the low voltage Vss based upon one or all of the input signals.
The dynamic logic circuit is only evaluated when the clock signal is high. That is, when the clock signal is high, the inverse of the voltage value (e.g., Vcc or Vss) on the dynamic node is the output of the circuit. Note that low signal or Vss is used to mean a logical zero (0) and high signal or Vcc is used to mean a logical one (1). Thus, dynamic logic circuits require some sort of a clocking mechanism in order to evaluate and transfer data.
FIG. 1 depicts a representative three-input OR-gate implemented using dynamic logic circuit technology. The circuit contains two PMOS devices (devices 112 and 114) and four NMOS devices (devices 102, 104, 106 and 108) and an inverter 110. PMOS device 112 is used as the pre-charging device and PMOS device 114 is used to maintain the voltage on dynamic node 116. For example, when the clock signal is low, PMOS device 112 will be turned on and thus will pre-charge the dynamic node 116 to Vcc. At line out 120, the voltage will be low due to inverter 110. This low voltage will turn the PMOS device 114 on, which will maintain the voltage on the dynamic node 116 at Vcc.
When the clock signal is high, NMOS device 108 will be turned on and PMOS device 112 will be turned off. If at that time one of the signals received at inputs a, b and c is high, the NMOS device that receives the signal will be turned on. Hence, the dynamic node will be discharged to Vss. At the line out 120, a high voltage will appear.
Early generations of dynamic logic circuits used a clock with a 50% duty cycle or pulse width. That is, 50% of the clock cycle was used as the evaluation phase where an operation would be performed and the other 50% of the clock cycle was used as a pre-charge phase. Consequently, only one operation was performed during each clock cycle. As faster and faster computing systems are designed, higher clock frequencies have become not only desirable, but required. Hence, various methods have been employed to increase frequencies of clock cycles.
One such method is to alter the duty cycle of the clock signal to either increase the evaluate phase and/or decrease the pre-charge phase while maintaining the smallest possible clock period. In this case, the maximum allowable frequency is limited to the setup and hold time requirements of the individual physical components that make up the dynamic digital logic circuit.
Another method that has been used in lieu of or in conjunction with the method described above is pipelining. In a simple pipeline configuration, a dual phase clock scheme is used. The dual phase clock includes generating a differential pair of symmetric clocks. Logic circuitries for implementing operations are divided into specific pipeline stages, whereby each stage uses one of the two clock phases. Specifically, when a pipeline stage performs an operation during an evaluate phase, the subsequent pipeline stage, which may depend on the output from the previous stage, is in its pre-charge phase. This simple pipelining configuration was disclosed in the related Patent Applications cited above.
In any event, since the duty cycle of a clock signal used to drive a dynamic logic circuit depends on the logic combination implemented in the circuit, different circuits may use different duty cycled clock signals. Hence, when a computing system consisting of a plurality of dynamic logic circuits is designed, different duty cycled clock signals may be used. This, then, will require clock signals of different pulse widths and/or separations to be correspondingly designed.
What is needed, therefore, is a variable pulse width and pulse separation generator.